Achieving flexible power management for embedded systems
Today’s embedded designers face increasing pressure to increase battery life while offering more features. One need only look at the rapid increase in functionality in wearable devices for verification. It has become clear that battery chemistry is not improving at the rate necessary to meet these requirements. This puts pressure directly on silicon suppliers to deliver better performance with lower power consumption. As if this dilemma isn’t challenging enough, designers are faced with stringent time-to-market requirements posed by shrinking design cycles.
In addition, environmental movements are calling for a reduction in battery waste, which translates into integrated systems that require fewer battery changes. There are also government regulations (Example: Energy Star) around the world to reduce standby current in home appliances. The next generation of embedded systems will require extremely low active and sleep power consumption while increasing the amount of flexibility and programmability needed to meet time-to-market requirements.
Aside from the lower current draw, there is also a need to reduce the system voltage. A few years ago the standard for minimum operating voltage was 3.3V. Today it is 1.8V. By tracing this trend, it is realistic to extend this trend to the subvolt range for tomorrow’s devices. This opens up the possibility of creating Psoc-based designs with a single AA battery (whose end-of-life voltage is around 0.9V). Although some Psoc-based designs can operate at 1.8 V today, very often analog performance degrades at such low voltages. For portable battery-powered designs that require good analog performance, systems that can operate on less than 1 volt voltage and still meet analog performance requirements offer the ability to switch to a single AA battery. This translates into lower cost to the consumer and fewer batteries.
How to achieve subvolt operation?
Undervoltage operation can be achieved when the built-in Psoc device has a built-in boost converter that can increase the input voltage (example: 0.9V input voltage) to a higher system voltage level (example: 3, 3 V). In this mode, it is important that the noise from the boost converter does not affect the performance of the analog peripherals. Figure 1 shows system-level connections for an integrated boost converter that is part of Cypress Semiconductor’s Psoc 3 programmable system-on-chip.
The Psoc 3 and Psoc 5 families are field-programmable embedded Psocs that have programmable digital blocks and configurable analog blocks. These devices are designed to offer flexibility and programmability to the user while consuming very little sleep and active current. The architectures also offer precise analog performance (16-bit to 20-bit precision). Families are supported by Psoc Creator software, an integrated development environment that can be used to rapidly develop end-to-end designs, from device selection, configuration/programming of digital and analog peripherals, system configuration power supply, firmware development, debugging and programming.
Having an integrated boost converter that can accept subvolt input voltages has the following advantages:
1. Ability to run the system on a single AA battery.
2. Ability to provide a guaranteed minimum system voltage even with variable supply voltage
3. Ability to use the boost output voltage to drive other circuits in the system that need a higher voltage. Example: LCD glass, sensor circuits, etc.
Wide supply voltage range
Having a wide supply voltage range that extends from 1.8 V (0.9 V with boost enabled) to 5.5 V provides maximum flexibility to the user due to the following reasons:
1. It can cover standard battery voltage ranges for the most common batteries up to the end of their useful life, as shown in table 1.
2. Compatible with 3.3V and 5V legacy system voltages.
3. The 5.5V high end provides headroom above 5V for rail-to-rail measurements of legacy system signals.
Wide external supply voltage, while maintaining a stable low core voltage for the silicon, can be achieved by providing built-in low dropout regulators within the device. Additionally, having separate internal regulators for digital and analog domains ensures that analog performance is not compromised due to noise from the digital power rails. Figure 2 shows the system level connections and internal regulators that accommodate a wide range of supply voltage.
Independent power supply for I/O banks
To allow connection to other devices in the system that may have different system voltages, a Psoc needs to have separate I/O power rails that can be independently configured to any voltage within a wide voltage range. A Psoc that has 4 I/O banks, with each I/O bank being able to operate on any voltage from 1.8V to 5V, provides seamless interface with other devices on the PCB
Flexible power modes
While the myth remains that programmable systems are power hungry, well thought out programmable Psocs can have world class power numbers to match standalone MCUs. Considering the end customer application, the power modes that are desirable
In Alternate Active mode, a selected smaller number of peripherals are active. This provides a reduced power active mode that can be entered from the normal active mode. Exiting this mode returns the system to normal active mode. An example use case for this is a situation where an integrated system with a display continues to function while the display alone is off. When the display needs to be turned off, the system will go into Alternate Active, where peripherals required for the display are turned off.
Sleep is a common usage mode in battery-powered embedded systems. This is an extremely low power mode, where all peripherals are in a low power state, while a real time clock can be maintained. This mode is also used for systems that need a constant duty cycle between active and asleep. An example use case is a temperature sensor that needs to update its reading every minute. The system wakes up every minute, takes the reading and goes back to sleep. This results in a reduced average power.
Hibernate is the lowest power consumption mode of the device, while the memory contents and settings can still be maintained. The ability to activate from an I/O source allows the user or another device in the system to activate the device. Hibernate mode can also be used to remove a power switch on a portable device (since the device can be woken up by any button press).
conclusion
A programmable Psoc offers high levels of integration while giving the user the ability to build their own custom peripherals using a highly configurable and programmable system. Carefully designed programmable Psocs can offer world-class power management features that not only meet MCU power numbers, but also offer a configurable power management system that can deliver precise analog performance as well.